Abstract
After forty years in the research labs, phase change memory reached a milestone in February 2008 when Intel Corp. announced it was sampling a 128Mb phase change memory (PCM) device. The milestone heralded a new phase in the long road to commercialization for phase change memories. The initial four years is expected to be the learning phase as vendors struggle to manufacture PCM in volume at high yields and OEMs modify firmware to take advantage of the fast performance and bit-alterability of PCM. However, a combination of aggressive advanced process technology transitions, physical cell size reduction and multi-level cell functionality is expected to accelerate cost reductions and make phase change memory a viable candidate to replace flash memory in the next five years. Phase change memory is forecast to growth at a compounded annual growth rate of 164% from 2008 to 2015 and account for 80% of the code flash market in 2015. Phase Change Memory Enters a New Phase outlines the challenges PCM faces as it vies to compete with mainstream charge-based memories. The report provides a thorough analysis of PCM versus current mainstream semiconductor memories such as SRAM, DRAM, NOR flash and NAND flash. An update on the PCM activities of major vendors as well as a market and price forecast out to 2015 based on a detailed roadmap is also provided.
Table of Contents
- CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- TERMINOLOGY
- EXECUTIVE SUMMARY
- MEMORY OVERVIEW
- Introduction
- The Memory Technology Hierarchy
- SRAM
- Concept
- Technology Evolution
- DRAM
- Concept
- Technology Evolution
- NOR Flash
- Concept
- Technology Evolution
- NROM
- Concept
- Technology Evolution
- NAND Flash
- Concept
- Technology Evolution
- PHASE CHANGE MEMORY
- Introduction
- Phase Change Material
- Memory Cell Concept
- Basic Operation
- Memory Cell Variations
- Selection Device
- PCM Characteristics
- Set Time
- Reset Current
- Endurance
- Memory Comparison
- Multi-level Cell PCM
- Device Layout
- PCM Reliability
- PCM Cost Drivers
- Die Size
- Process Complexity
- Technology Scaling
- Scaling Parameters
- Roadmaps
- PCM DEVELOPMENT STATUS
- PCM Development Status
- ATMI, Inc.
- BAE Systems
- CAMELS
- Elpida
- Hynix Semiconductor
- IBM
- IMEC
- ITRI
- Macronix International
- Nanochip
- Numonyx (Intel/ST)
- NXP Semiconductors
- Ovonyx
- Qimonda AG
- Renesas Technology
- Samsung Electronics
- STMicroelectronics
- ULVAC
- MARKET FORECAST
- Applications
- Market
- REFERENCES
- ABOUT THE AUTHOR
- ABOUT FORWARD INSIGHTS
- Services
- Contact
List of Figures
- Figure 1. Memory Hierarchy
- Figure 2. SRAM Cell Layout
- Figure 3. 3D SRAM Technology
- Figure 4. DRAM Cell
- Figure 5. DRAM Cell Transistor Evolution
- Figure 6. DRAM Cell Capacitor Trend
- Figure 7. NOR Flash Cell
- Figure 8. NOR Architecture
- Figure 9. NOR Flash Cell
- Figure 10. NOR Flash Technology Evolution
- Figure 11. Drain Bias Margin
- Figure 12. NROM Cell Concept
- Figure 13. NROM Architecture
- Figure 14. NROM Cell
- Figure 15. NROM Technology Evolution
- Figure 16. Bit Disturb ("Second Bit Effect")
- Figure 17. NAND Flash Cell Concept
- Figure 18. NAND Architecture
- Figure 19. NAND Cell String
- Figure 20. NAND Flash Technology Evolution
- Figure 21. NAND Flash Memory Gap Fill
- Figure 22. Electrons Stored on the Floating Gate
- Figure 23. Samsung 32Gb CTF Memory
- Figure 24. Timeline of Phase Change Memory
- Figure 25. Periodic Table
- Figure 26. GST Composition
- Figure 27. Basic PCM Cell Structure
- Figure 28. Set Operation
- Figure 29. Reset Operation
- Figure 30. Phase Change Memory I-V Curve
- Figure 31. Memory Array Operation
- Figure 32. µTrench and Lance Structures
- Figure 33. Lance and pore structure
- Figure 34. Phase Change Bridge Memory
- Figure 35. MOS and BJT Selector
- Figure 36. Diode Selector
- Figure 37. Set Time Trend
- Figure 38. Dependence of Reset Current on Contact Area
- Figure 39. Reset Current Reduction with Ta2O5 Interfacial Layer
- Figure 40. Reset Current Trend
- Figure 41. PCM Endurance
- Figure 42. Read Access Time Comparison
- Figure 43. Write Throughput
- Figure 44. Program Performance Comparison
- Figure 45. MLC Write Approaches
- Figure 46. MLC Distribution
- Figure 47. Multi-level States as a Function of Pulse Tail
- Figure 48. 16-Level and 4-Level PCM
- Figure 49. Samsung Phase Change Memory Device Evolution
- Figure 50. Samsung 90nm 512Mb PRAM Layout
- Figure 51. ST/Intel Phase Change Memory Device Evolution
- Figure 52. NOR Flash and PCM Architecture
- Figure 53. Intel 256Mb 130nm 28F256L18 StrataFlash Organization
- Figure 54. 128Mb (256Mb MLC) PCM Organization
- Figure 55. Endurance as a function of Energy per Pulse
- Figure 56. PCM vs. NOR Flash
- Figure 57. Phase Change Memory Technology Evolution
- Figure 58. Samsung PRAM Cell Size Evolution
- Figure 59. SABEC Process
- Figure 60. PRAM Module
- Figure 61. 180nm Process µTrench PCM Process
- Figure 62. Phase Change Memory withµTrench Cell
- Figure 63. Scaling Parameters
- Figure 64. PCM Scaling Challenges
- Figure 65. Memory Roadmaps
- Figure 66. Bit Size Trend
- Figure 67. Density Trend
- Figure 68. Areal Density Trend
- Figure 69. Embedded PCM Roadmap
- Figure 70. U.S. PCM Patents from 1990 to January 2007
- Figure 71. Radition-hard C-RAM
- Figure 72. Memory Device Characteristics - 2012
- Figure 73. PCM in the Memory System
- Figure 74. PCM as an Unified Memory
- Figure 75. PCM in the Memory Hierarchy
- Figure 76. $/MB Forecast
- Figure 77. PCM NOR Replacement Rate
- Figure 78. Memory Revenue Forecast
